DESIGN OF 32 BIT SINGLE PRECISION FLOATING POINT MULTIPLIER USINGVEDIC MATHEMATICS

Authors

  • Ms.Radhika Jumde U.G Dept Of ENTC,AVBIT, Pawnar,Wardha
  • Ms.Gauri Jambhulkar U.G Dept Of ENTC,AVBIT, Pawnar,Wardha
  • Ms.Megha Chalakh U.G Dept Of ENTC,AVBIT, Pawnar,Wardha
  • Ms.Dhanashri Bhagat U.G Dept Of ENTC,AVBIT, Pawnar,Wardha

Keywords:

Carry Save Adder, IEEE 754, Urdhva-Triyakbhyam sutra, Vedic Mathematics, VHDL, Xilinx

Abstract

This project presents a 32-bit single precision floating point multiplier based on Vedic mathematics. To improve delay a new algorithm called Urdhva-Triyakbhyam will be design for the multiplier design. By using this approach number of components will be decreased and complexity of hardware circuit will also be decrease. In this project, Vedic multiplication technique will be used to design IEEE 754 floating point multiplier. The Urdhva-Triyakbhyam sutra is used for the multiplication of Mantissa i.e. 24x24 bits. The sign bit of the result is calculated using one XOR gate and a Carry Save Adder is used for adding the two biased Exponents. The underflow and overflow cases are handled. The inputs to the multiplier are provided in IEEE 754 i.e. 32 bit format. The multiplier will be design, synthesize and stimulate in VHDL using Xilinx ISE tool. 

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Published

2016-05-20

How to Cite

Ms.Radhika Jumde, Ms.Gauri Jambhulkar, Ms.Megha Chalakh, & Ms.Dhanashri Bhagat. (2016). DESIGN OF 32 BIT SINGLE PRECISION FLOATING POINT MULTIPLIER USINGVEDIC MATHEMATICS. International Engineering Journal For Research & Development, 2(3), 5. Retrieved from http://www.iejrd.com/index.php/ /article/view/520

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