DEVELOPMENT OF ATPG USING BASICALGORITHM PROCESSES

Abstract

To test the functioning of the fabricated circuit (IC) Automatic Test Pattern Generator (ATPG) is becoming increasingly important as designs become more complicated. Over the years ATPG tool development process is the research interest for testing the VLSI circuits. ATPG tool development mainly comprises of the three processes if we consider the Deterministic Test Pattern Generation part, which are Fault Equivalence, Line Justification, Fault Propagation. In this paper, all processes are implemented for the combinational circuit with some limitations. Considering the single stuck-at faults, the fault list becomes lengthy as the circuit under test has a large number of nets. To reduce the total number of faults to be tested Fault Equivalence method is used. Testability measure means finding out Controllability and Observability of a circuit. Controllability helps us to find out the easily controllable net during the line justification process. The actual test vector generation of every fault has the two most important processes that are Line justification and Fault propagation. In this paper codes written for fault equivalence, controllability, line justification, and fault propagation in Perl language for 2 fanin-fanout gates. All developed programs are generic and can be used for any combinational circuit which has non reconvergent fanouts. For all processes, the input required is the circuit netlist file (.txt file). All program works dynamically i.e. it also gives correct results if the circuit netlist is not in the order of input to output direction. For reconvergent fanout, it has limitation i.e. to generate the test vector for the fault which require backtracking. For the rest of the faults, it works fine.