DELAY COMPARISON OF BOOTH MULTIPLIER AND VEDIC MULTIPLIER USING VHDL

Abstract

called multiplier. If the delay of the multiplier is reduced then the speed of the processor automatically gets increased. This paper presents design of Booth Multiplier and Vedic multiplier using VHDL (Very High Speed Integrated Circuit Hardware Description Language). Booth multiplier has been designed by using the Booth algorithm concept. Vedic multiplier has been designed by using Vedic mathematics. There are total 16 Sutra’s, out of which Urdhva Tirvakbhyam (Vertically and Crosswise) Sutra is used for designing the Vedic multiplier. After designing these two multipliers, delays are compared to know the efficient multiplier. The code is written in VHDL Language and simulation is done in Xilinx 13.1 i.