DESIGN OF HIGH PERFORMANCE 32-BIT CRYPTOGRAPHIC PROCESSOR

Authors

  • Jayarajesh Vattam Asst.Prof, ARMIET,Shahapur.Thane,Maharashtra, India-421601
  • Sheetal Jagtap Asst.Prof, ARMIET,Shahapur.Thane,Maharashtra, India-421601
  • Sankaraiah Mogaligunta Asst.Prof.,NBKRIST,Vidyanagar, SPSR Nellore, AP, India-524413

Keywords:

Cryptographic-processor, reconfigurable architecture, finite field arithmetic (FFA), modular addition

Abstract

With rapid increases in communication and network applications, Cryptography has become a crucial issue to ensure the security. In this proposed paper a microcode-based architecture with a novel reconfigurable data path which can perform either prime field operations or binary extension field operations for arbitrary prime numbers, irreducible polynomials and precision. The proposed embedded cryptographic Processor architecture could achieve full cryptography algorithm flexibility, High hardware- utilization and High Performance.In particular ASIC solution generally leads to a higher throughput rate at a lower cost, but it is inflexible. To mitigate the gap between GPP & ASIC realizations, application-specific cryptographic processors have been proposed, each with its own instruction-set architecture, data path design and target applications.

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Published

2016-03-20

Issue

Section

Articles

How to Cite

[1]
“DESIGN OF HIGH PERFORMANCE 32-BIT CRYPTOGRAPHIC PROCESSOR”, IEJRD - International Multidisciplinary Journal, vol. 2, no. 2, p. 9, Mar. 2016, Accessed: Sep. 30, 2026. [Online]. Available: https://www.iejrd.com/index.php/iejrd/article/view/498

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