2D MESH TOPOLOGY USING ROUTING ALGORITHMS FOR NOC ARCHITECTURE

Abstract

As per the recent studies, the development of integration technology, System on-Chip (SoC), has large number of transistor. As the microprocessor industry is moving from single-core to multicore architectures, which require efficient communications processors. Also both SoC and microprocessor are used for a highperformance, flexible, scalable, and design-friendly interconnection. Interconnection architectures are usually based on dedicated wires or shared buses. NoC has been proposed as a highly structured and scalable solution to address communication problems in SoC. Onchip interconnection network provides advantages over dedicated wiring and buses, i.e. high-bandwidth, low-latency, low-power consumption and scalability. Among these topologies, mesh topology has gained more consideration by designers due to its simplicity. In this paper, we compare source routing algorithm and junction based routing algorithm using 2D mesh topology of NoC architecture in terms of different performance metrics such as, latency, power consumption, and power/throughput ratio.