DESIGN OF DYNAMIC PARITY BASED ARBITER FOR NoC ROUTER

Abstract

NoC means Network on Chip is a new method for communication to solve a problem that challenges system on chip. Network-on-Chip (NoC) is an appealing alternative for communication in SoCs with ability of providing high throughput, low latency and scalability. Using a network to replace global wiring has advantages of structure, performance, and modularity. NoC architecture has two parts: router and data link. The router is a module which can use to store and forward data, and the data link use to transmit signals from one router to its neighbour. And router consist of three part such as input buffer, arbiter, and crossbar. Dynamic priority of a packet is given according to the traffic load of previous router. In certain router, if many packets request the same output channel, the router need to choose one of these packet, and deliver it to next router. In the dynamic priority based round robin arbiter in this they can reduced power consumption and area gate count. The dynamic priority based matrix arbiter and also compare the parameter like area, Power consumption and delay, which we will improve the speed of communication
on NoC router. After designing and synthesis of both the arbiter it has been observed that power of matrix arbiter found to be less so Matrix arbiter is more power efficient than Round Robin Arbiter. Along with reduced the number of gate counts ,which can be used to calculate approximated area and also reduction in delay which we will improve the speed of communication on NoC router.